This invention relates to integrated circuit devices, and more particularly to integrated circuit devices coupled to multiple power supplies, that include power detection circuitry.
With the advent of high speed and low power applications for integrated circuit devices, integrated circuit devices have been developed that are supplied with currents from power supplies of different voltages. Generally, core processing logic within programmable logic devices is powered with lower voltage power supplies, and I/O (Input/Output) drivers that drive external signals are powered with higher voltage power supplies. For example, circuits within one integrated circuit device may be implemented with TTL (transistor-transistor logic), in which a logic-1 signal is nominally at 5 volts, while a logic-0 signal is nominally of zero voltage; LVTTL (Low Voltage TTL, which exists in a 3.3-volt version or a 2.5-volt version); PCI (Peripheral Component Interface, which may require a 3.3-volt power supply); SSTL (Series Stub Terminated Logic, which has several variants); GTL (Gunning Transceiver Logic); GTL+; and HSTL (High Speed Transceiver Logic, which has several variants). Additional signaling schemes that are based on other voltage levels have been developed, and continue to be developed.
Indication of whether all power supplies to an integrated circuit device have reached functional voltage levels may be useful for various applications. One application is to keep circuits within the integrated circuit device inactive through application of an internal reset signal that is further qualified by a signal that indicates whether all power supplies to the integrated circuit device have reached full/nominal rail levels, thereby preventing damage to the circuits. Therefore, it may be desirable to provide integrated circuit devices that include power detection circuits that indicate whether power supplies have reached functional voltage levels.
Integrated circuits, such as PLDs, in accordance with this invention include power detection circuits that indicate whether power supplies coupled to the integrated circuits have reached functional voltage levels. The power detection circuits typically include various latches, well bias circuits, and logic circuits that provide output signals to indicate whether power supplies that are being monitored have reached functional voltage levels.
In accordance with the principles of the present invention, a preset latch may be coupled to some clear latches that control the output of the power detection circuit. The preset latch controls the clear latches, and thus the output of the power detection circuit, when the monitored power supplies have not reached functional voltage levels. Under these conditions, the power detection circuit outputs a first logic level, indicating that the power supplies have not reached functional voltage levels.
When all power supplies monitored by the power detection circuit have reached functional voltage levels, the preset latch may be turned off, and the clear latches may then control the output signal of the power detection circuit. Under these conditions, the power detection circuit outputs a second logic level, indicating that the power supplies have reached functional voltage levels. Various logic circuits may be used to couple the preset latch with the clear latches. These logic circuits may be arranged for redundancy so that at least one logic circuit is powered up when a first power supply is at functional voltage level. Well bias circuits may be used to achieve this result.
Applications of power detection circuits include using the output signals of power detection circuits to condition reset signals, thereby holding integrated circuit devices in reset until power supplies have reached functional voltage levels. Circuits may be provided in accordance with the present invention that condition reset signals with outputs from power detection circuits so that a reset signal may be generated that is conditional upon power supplies reaching functional voltage levels.